The demand for semiconductor integrated circuit (IC) devices such as computer chips with high circuit speed and high circuit density requires the downward scaling of feature sizes in ultra-large scale integration (ULSI) and very-large scale integration (VLSI) structures. The trend to smaller device sizes and increased circuit density requires decreasing the dimensions of interconnect features and increasing their density. An interconnect feature is a feature such as a via or trench formed in a dielectric substrate which is then filled with metal, typically copper, to yield an electrically conductive interconnect. Copper, having better conductivity than any metal except silver, is the metal of choice since copper metallization allows for smaller features and uses less energy to pass electricity. In damascene processing, interconnect features of semiconductor IC devices are metallized using electrolytic copper deposition.
In the context of semiconductor integrated circuit device manufacture, substrates include patterned silicon wafers and dielectric films such as, for example, SiO2 or low-κ dielectrics. Low-κ dielectric refers to a material having a smaller dielectric constant than silicon dioxide (dielectric constant=3.9). Low-κ dielectric materials are desirable since such materials exhibit reduced parasitic capacitance compared to the same thickness of SiO2 dielectric, enabling increased feature density, faster switching speeds, and lower heat dissipation. Low-κ dielectric materials can be categorized by type (silicates, fluorosilicates and organo-silicates, organic polymeric etc.) and by deposition technique (CVD; spin-on). Dielectric constant reduction may be achieved by reducing polarizability, by reducing density, or by introducing porosity.
A patterned semiconductor integrated circuit device substrate, for example, a device wafer or die, may comprise both small and large interconnect features. Typically, a wafer has layers of integrated circuitry, e.g., processors, programmable devices, memory devices, and the like, built in a silicon substrate. Integrated circuit (IC) devices have been manufactured to contain small diameter vias and sub-micron sized trenches that form electrical connections between layers of interconnect structure. These features have dimensions on the order of about 150 nanometers or less, such as about 90 nanometers, 65 nanometers, or even 45 nanometers.
Plating chemistry sufficient to copper metallize small size via and trench features has been developed and finds use in the copper damascene method. Copper damascene metallization relies on superfilling additives, i.e., a combination of additives that are referred to in the art as accelerators, levelers, and suppressors. These additives act in conjunction in a manner that can flawlessly fill copper into the interconnect features (often called “superfilling” or “bottom up” growth). See, for example, Too et al., U.S. Pat. No. 6,776,893 and Commander et al., U.S. Pub. No. 2003/0168343, the disclosures of which are hereby incorporated as if set forth in their entireties. Currently available electrolytic copper deposition systems that rely on superfilling additives can fill small size features at current densities as high as 6 A/dm2 and in as little as 20 seconds, 10 seconds, or less.
In another form, a wafer may be constructed to comprise one or more large diameter vias. This type of via architecture is known in the art as a “through silicon via” (TSV). In some devices, through silicon via allows electrical interconnection between 2 or more wafers bonded to each other in a three-dimensional wafer stack. After being formed, the 3D wafer stack may be diced into stacked dies (“chips”), each stacked chip having multiple tiers (“layers”) of integrated circuitry. Depending on where and when the vias are made, they can be characterized as “Via First—Before FEOL”, or “Via First—After BEOL”. In both cases, the vias are made before wafer/die attachment or bonding. The third category of TSV is via last, which means the via is constructed after wafer/die attachment or bonding.
Through silicon vias are critical components of three-dimensional integrated circuits, and they can be found in RF devices, MEMs, CMOS image sensors, Flash, DRAM, SRAM memories, analog devices, and logic devices.
The depth of a TSV depends on the via type (via first or via last), and the application. Via depth varies from 20 microns to 500 microns, typically between about 50 microns and about 250 microns. Via openings in TSV have an entry dimension such as a diameter on the order of between about 200 nm to about 200 microns, typically between about 25 microns and about 75 microns. The typical aspect ratio for a through silicon via is from 0.3:1 to greater than 20:1.
Filling large size through silicon via in commercially practicable durations is a barrier to the commercial feasibility of devices employing TSV. Experimental data obtained to date suggests that conventional electrolytic copper deposition methods employing compositions appropriate for damascene metallization (i.e., the composition comprises the three component superfilling additives including accelerator, suppressor, and leveler) are current density limited (such as about 0.10 A/dm2 or less to get defect-free fill) and may require plating durations as long as 20 hours to completely metallize large dimension (e.g., greater than 50 micron diameter openings) through silicon via.
Available prior art in the field of through silicon via filling has not, to date, suggested methods and compositions capable of rapidly filling through silicon via in a commercially practicable deposition period.
For example, Arana et al. (U.S. 2007/0001266, Intel Corporation) disclose a method for filling through silicon via by incorporating particles into the copper metallization, the particles having a different coefficient of thermal expansion than the copper matrix. The stated purpose is to reduce stress variations between the copper metallization matrix and the silicon possibly caused by the differing bulk CTE of the respective materials. Notably, the reference does not include actual electrolytic copper plating chemistry, nor does the reference state that their electrolytic plating method incorporating particles in the deposition composition reduces through silicon via fill time.
Lane et al. (U.S. Pat. No. 7,081,408, Intel Corporation) disclose a method for filling through silicon via features. Although they discuss filling the through silicon via with copper metallization by any suitable process, for example, electrolytic deposition, Lane et al. do not disclose actual electrolytic copper plating chemistry, nor do they disclose the duration necessary to achieve copper filling.
Copper plating is also known from, e.g., also Eilert (U.S. Pat. No. 7,111,149); Rumer et al. (U.S. Pat. No. 6,924,551); Shi et al. (U.S. Pub. No. 2007/0085198); Ramanathan et al. (U.S. Pub. No. 2007/0117348) Heck et al. (U.S. Pub. No. 2006/0264029); Williams et al. (U.S. Pub. No. 2006/0273455); Rangel (U.S. Pub. No. 2006/0278979); and Savastiouk et al. (U.S. Pub. No. 2005/0136635); but none of these references, which relate to through silicon via architectures and methods, disclose applicable copper metallization chemistries or plating durations sufficient to fill through silicon via features.
Given the current state of the art, it is apparent that there is a distinct need for applicable methods and compositions sufficient to copper metallization through silicon via features in a commercially practicable manner.